tag:blogger.com,1999:blog-25419333059811963982024-03-14T05:30:51.840+00:00CPC FPGAThe smallest Amstrad CPC emulator - a custom designed re-programmable FPGA board by <a href="http://www.ranulf.net/">Ranulf Doswell</a>.Unknownnoreply@blogger.comBlogger64125tag:blogger.com,1999:blog-2541933305981196398.post-84992175961936494442016-06-13T12:18:00.001+01:002016-06-13T13:13:03.258+01:00BarCamp Birmingham 2016<p>This weekend, I went to the BarCamp Birmingham event.</p>
<p>BarCamp is organised by FLOSS UK (Free Libre Open Source Software) and is run in an unconference style, much like our monthly engineering openspaces, people write down on Post-It notes something they'd be prepared to talk about or that they'd like to learn about, then they're voted on and talks are done in order of everyone's preferences.</p>
<p>It's a single day event, running from 10am to 5pm with about 30 attendees, followed by a pub trip afterwards. Unusually, for this kind of event it's free and food is provided. The venue has been the same for the last few years, just a few minutes walk from New Street station in Birmingham. There's a bit more information available at <a href="http://www.flossuk.org/events/barcamp-birmingham/">http://www.flossuk.org/events/barcamp-birmingham/</a></p>
<p>The talk structure is roughly 20 minutes including Q&A, although some of the things people want to learn about are done instead as a BOF group (Birds Of a Feather) where 3 or 4 people chat together whilst other people are in different groups or eating lunch etc. Some people have presentations they've used elsewhere, others were totally off the cuff.</p>
<p>In previous years, there was a lot more focus on open source, this year it felt more like it was related to people's interests and current projects. There's a heavy UNIX bias though, I think I was the only one with a Windows laptop for instance!</p>
<p><h1>Talk 1 - Tactile Internet (Indria)</h1>
This was a talk from someone who'd just joined a research group a few weeks ago looking at low latency remote working, so things like surgeons operating in different countries to the patient, etc. Think like a bomb defusal robot except a lot more realtime and tactile feedback, e.g. being able to feel the knife you've just picked up, and quick response.
<p></p> Interestingly, this all seems to be based on 5G phone tech and is aiming for 1ms round-trip time (which is amazing given the expectation that this would work across the globe). Lots of stuff from routing problems like reducing the size of packet headers to reduce latency, to high availability, to just how to have the correct physical response so a real-life expert isn't impeded, etc.</p>
<p><h1>Talk 2 - Cloud ABI (Alex Willmer @moreati)</h1>
<p></p> Describing managing "capabilities" in operating systems, to enable trust of downloaded executables.
<p></p> Based on "capsicum" project for FreeBSD, see <a href="https://github.com/NuxiNL">https://github.com/NuxiNL</a>
<p></p> Idea is essentially to remove system calls from OS layers, so e.g. the executable is passed already open file handles or a filehandle to a directory rather than a filename and have it open the right itself.
<p></p> Goes beyond FreeBSD's pledge() call because it's not opt-in and the library functions aren't even available at compile time, making it harder to accidentally use unsafe APIs.
<br> Implemented on Linux via binfmt_misc (a way of emulating different OS personalities)
<br> It wasn't explicitly mentioned in the talk, but I thought there were good parallels for TDD and injection too.</p>
<p><h1>Talk 3 - Hacking your body (Adam Sweet)</h1>
A compressed version of the hour talk he gave at Oggcamp in Oxford a year or two ago (also a great event!)
<p></p> He just covered diet in this, not the fitness part and how to look after your back, that he covered then.
<p></p> Basically, fat doesn't make you fat, sugar does.
<p></p>He went less far than the low-carb books I've read, he advocates just a balanced mix of protein, carbs and fat, and his main emphasis is on cooking your own food rather than buying stuff with things added to make them taste more appealing (usually sugar!)</p>
<p><h1>Talk 4 - Demoscene (Ralf)</h1>
I gave a talk about the demoscene.
<p></p>Started off by showing them <a href="https://www.youtube.com/watch?v=ANjqurREBpw">Gaia Machine by Approximate</a> which won the 64KB compo in Revision 2012. Afterwards I asked them to guess how big the code was for the 4:30 demo. A few people jumped the gun at 4KB!
<p></p>I also showed them a quick snippet of <a href="https://www.youtube.com/watch?v=6CiF034IhgY">Felix's Workshop</a> which came 2nd in the same 64KB compo to show them that small demos weren't always really abstract.
<p></p>After talking a bit about PC demos and the different types of compo (4KB, 16KB, music, unlimited), I then mentioned others like retro and wild and showed a snippet from my <a href="https://www.youtube.com/watch?v=G8sxnxnAyH0&t=14m20s">Breaking Baud</a> demo.</p>
<p><h1>Talk 5 - Agile (Steve Pitchford @stevejpitchford)</h1>
He gave a talk on Agile development, focussed mainly on how Agile is usually applied as a set of rules to follow rather than as a bias towards agile methods, and how a lot of projects fail because they try to throw out their old style of working as well. He pointed out that the most common word in the <a href="http://www.agilemanifesto.org/">Agile Manifesto</a> is over, as in "we value X over Y", not "do X not Y".
<p></p>He mentioned <a href="https://en.wikipedia.org/wiki/Two-factor_theory">Herzberg's two-factor theory</a> as an advanced form of the Maslov's hierarchy of needs that most of us are familiar with; essentially what motivates and demotivates people in work.</p>
<p><h1>Talk 6 - Animation using Continuous Integration (Mike Hingley @computa_mike)</h1>
Mike and <a href="http://titaniumbunker.com/">his brother</a> had created a children's animation based on a story from a 7-year old kid, about <a href="https://www.youtube.com/watch?v=cul1CAh_Pio">a dragon who stole the Queen's money and featured a cat detective</a>!
<p></p>The animation was created entirely using open source software and had decided to use continuous integration (Jenkins CI) to render the animation on commits.
<p></p>He mentioned some of the technical hurdles - Kdenlive used absolute paths, so needed a helper program to be written to modify the paths before commit and after getting latest, and moving to incremental renders where only modified scenes were re-rendered on commit and injected to the correct place in the animation.
<p></p>They used git, but didn't have large binaries as their files were mostly XML 2D SVG, but his brother was new to git and used <a href="https://git-cola.github.io/">git-cola</a> which they found gave him a very good process and way into git.
<p></p>The animation itself was made with <a href="http://www.synfig.org/cms/">Synfig</a>
<p></p>All of his animation source assets are open and <a href="https://github.com/computamike/scargo">available on github</a></p>
<p><h1>Talk 7 - Databases (Brian Walker)</h1>
<p></p>Brian works for HSBC as a DBA responsible for some massive databases, e.g. a 75TB database held across 6 servers, and described some of the thought processes he went through when somebody asked him to spec out hardware for a database.
<p></p>The example he used was a 2TB database. I forgot to make detailed notes, but some of the considerations were:
<p></p>Roughly another 500MB for temporary space was needed - database performance would be massively reduced without the extra space for the DB to use when regenerating indices etc.
<p></p>He would typically start with 6 PCI slots and 6 drive bays, and use 2 drives for tables and 1 for database indexing use. Those 2 table drives would be either primary or secondary tables or split between primarily read and primarily write with a slower background process shunting new data to the read disk. He'd then use the other 3 drives to do RAID on the data.</p>
<p><h1>Talk 8 - Calendar integration with Office 365 (John Knight)</h1>
<p></p>He was focussed on the Graph API, which is RESTful, but said that it's actually the same API as shared with OneDrive, the Directory Service, etc.
<p></p>Turns out to be remarkably easy, also the OAuth2 tokens can be used with the other protocol (I wasn't paying enough attention here!) and also commented that whilst there was both a released and a beta API, and they both kind of worked, they were both felt a bit alpha quality in that he was never really sure if something would work or not without trying it. But on the whole, it was successful and they imported something like 10,000 users worth of calendars this way.
<p></p>There was a comment about not having permissions to do certain operations because even though the systems admin had set the policy to allow it, because the user can't given authentication they couldn't do some operations. Apparently this is a bug that is being fixed, but until then it's hard to do some things on their user's behalf.</p>
<p><h1>Talk 9 - The Julia programming Language (Keith)</h1>
<p></p>Seems like an interesting language that's gaining popularity with scientific users, being faster than Fortan and not much slower than C.
<p></p>The official website is <a href="http://julialang.org/">http://julialang.org/</a>
<p></p>There's a sandbox where you can play with the language over the web with no installation, <a href="https://juliabox.org/">https://juliabox.org/</a> which itself seems to have been built with <a href="http://jupyter.org/">Jupyter Notebook</a>.
<p></p>The language itself seems quite dynamic and has a whole load of libraries for numerical simulation, stats and plotting graphs etc that seem pretty trivial to use.
<p></p>There's an interactive REPL for trying out ideas and it seems to use LLVM for the original purpose, as a low-level virtual machine, so it can compile quickly but also optimise programs on the fly as the execution hotspots are discovered.
<p></p><a href="https://cloud.sagemath.com/">SageMathCloud </a>was mentioned, not sure what it is, but it looks very interactive</p>
<p><h1>Talk 10 - First hand experiences with the HP detachable - hybrid laptop / tablet (Quentin Wright)</h1>
Discounted the surface due to difficulty of typing on your lap, the HP has a nice keyboard that's detachable but appears as a USB device when plugged in.
<p></p>Had some issues with Win10, despite it being one of the Microsoft Flagship Laptops and purchased from the MS Store. Eventually upgraded to Ubuntu, discovered that KDE was very badly set up for tablet use, but Gnome was very useable. </p>
<p><h1>Talk 11 - Writing a vim plugin (Nick Morrott @nickmorrott)</h1>
Nick maintains a database of TV programme descriptions for MythTV users and this database is in a text file (around 7500 lines) with a few different fixed formats.
<p></p>Whilst this talk was vim-specific, it was more about the general approach to making common tasks easier and could also be applied to emacs (and presumably VS via a plugin).
<p></p>He referred to the paper "<a href="http://www.moolenaar.net/habits.html">Seven habits of effective text editing</a>" by Bram Moolenaar (the author of vim) which describes a lot of the ideas which drove his development of vim.
<p></p>Nick went through how to set up a plugin for vim (basically, use one of the many vim plugin managers), and then showed us the code for his syntax highlighter, the code for various utility functions (e.g. create a new type-3 entry) and how to assign them to key-bindings, and finally a syntax checker than automatically highlighted syntax errors as the document was edited.
<p></p>The syntax checker itself was a perl script, so could also be used as a git pre-commit script with minimal changes, so preventing bad data ever being checked into the repository.
<p></p>His plugin and associated utilities are here: <a href="https://github.com/knowledgejunkie/vim-xmltvfixup">https://github.com/knowledgejunkie/vim-xmltvfixup</a></p>
<p><h1>Talk 12 - Introduction to FPGAs (Ralf)</h1>
After explaining what the acronym stands for and then explained that in less obtuse terms, I gave a background on the history of why FPGAs are useful, from late 70s/early 80s computer design where glue logic would take up more board space than the CPU and peripherals, to machines like the ZX Spectrum with its ULA (about 100 gates), to PLAs, ASICs and then FPGAs and gave an idea of the scope of what you can do with them.
<p></p>Showed a slide from my emulation talk, showing a typical cell, and explained what the elements did and then mentioned things like the embedded RAM blocks and hardware multipliers and different kinds of IO ports available.
<p></p>Ended with the couple of slides showing basic VHDL for adding and multiplying two 16 bit numbers and a snippet of my code showing how bigger chunks of code can look quite high-level.</p>
<p><h1>Finally...</h1>
There were probably another 5 topics that we didn't have time to cover and a bunch of want-to-knows that were somewhat covered in smaller BOF groups over lunch, including an introduction to Arduino and how to debug python.</p>
<p>I also proposed 2 more topics myself - "DIY Quadcopters" (which received a lot of votes, but not quite enough to do before we ran out of time) and "What it's like working in the games industry Q&A" (which received only 2 votes).</p>
<p>I had a couple of good conversations about retro computing preservation, Haskell versus Ocaml and quadcopter flight controllers.</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com3tag:blogger.com,1999:blog-2541933305981196398.post-19094080551777571502015-08-11T19:01:00.001+01:002015-08-11T19:01:34.703+01:00Quadcopter funI recently bought a new quadcopter, so today I started a blog about it: <a href="http://quad.ranulf.uk">quad.ranulf.uk</a>
<p>
Sadly, it'll be a bit quiet for a couple of days as after 7 days of practice and getting to grips with it and without serious incident, today I tried the acrobatic mode and 5 seconds later it was a crumpled mess embedded in the soil. Ooops. Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com1tag:blogger.com,1999:blog-2541933305981196398.post-2152309807619900442015-06-20T18:19:00.000+01:002015-06-20T18:30:00.084+01:00Rare Replay announced at E3<p>So, one of the reasons I've been quite quiet for the last few months (and didn't have time to make a demo for Revision) is that I've been incredibly busy at work... And at last after months of secrecy, the game was announced at E3, called "Rare Replay":</p>
<p><iframe width="560" height="315" src="https://www.youtube.com/embed/AaieVt3M72c" frameborder="0" allowfullscreen></iframe></p>
<p>As you can see, it's right up my street and it's been a lot of fun working on this project! :)</p>
<p>The other game we're working on at Rare was also announced, "Sea of Thieves":</p>
<p><iframe width="560" height="315" src="https://www.youtube.com/embed/1z48qvGsA_0" frameborder="0" allowfullscreen></iframe></p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com1tag:blogger.com,1999:blog-2541933305981196398.post-64764745180360056062015-04-13T22:31:00.002+01:002015-04-13T22:39:26.107+01:00Why you should write an emulator<p>Here's my talk from Revision 2015:</p>
<iframe width="853" height="480" src="https://www.youtube.com/embed/Hh-SGKl_qWA" frameborder="0" allowfullscreen></iframe>
<p>There's also a whole load of other <a href="https://www.youtube.com/user/RevisionParty/videos">seminars and compos</a> to watch too... :)</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com1tag:blogger.com,1999:blog-2541933305981196398.post-71886279326399270952015-04-07T23:32:00.000+01:002015-04-07T23:39:43.815+01:00Breaking baud videoBreaking Baud... just realised that it's almost a year after the fact and I've still not uploaded a proper capture of the final version of Breaking Baud. So, the best quality capture is still <a href="https://www.youtube.com/watch?v=G8sxnxnAyH0&t=14m20s">the official livestream</a>... :)
<iframe width="853" height="480" src="https://www.youtube.com/embed/G8sxnxnAyH0?start=860" frameborder="0" allowfullscreen></iframe>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-27717455227770882122015-04-04T17:07:00.002+01:002015-04-13T23:00:04.807+01:00Seminar at Revision 2015Eeeks, so I realised that I've been too busy to post a single blog entry since Revision last year. Ooops!
Anyway, today I presented a seminar at this year's Revision called "Why you should make an emulator". I'll provide a youtube link when available, but for now you can check out <a href="http://voxel.angrysprite.com/public/why_make_emulator/Why%20you%20should%20try%20to%20make%20an%20emulator.pptx">the slide deck</a> and just imagine that it's the best presentation you've ever heard! :)Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-56033566199308377912014-04-22T12:39:00.001+01:002014-04-22T12:41:09.855+01:00Breaking Baud - 2nd place in the Revision Oldskool demo competition<p>
So, one of the reasons I've not been making much progress recently on the FPGA is that I've spent the last couple of months working on a new tape turbo load system for the Amstrad CPC.
</p>
<p>
The result is here (warning, don't turn up too loud until you get a feel for the volume of the loading sounds!):
</p>
<p>
<iframe width="560" height="315" src="//www.youtube.com/embed/D62jpqZ6TG4" frameborder="0" allowfullscreen></iframe>
</p>
<p>
I'm proud to say it came 2nd in the Oldskool competition, stacked up against some very worthy competition. Many thanks to JulijanaM and rexbeng for their beautiful artwork and McKlain for his amazing tunes!
</p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-6020768473055517422014-04-02T09:31:00.003+01:002014-04-02T09:31:53.195+01:00Silicon exposed blogI've just discovered these awesome posts via Hackaday:
<ul>
<li><a href="http://siliconexposed.blogspot.co.uk/2014/03/getting-my-feet-wet-with-invasive.html">Getting my feet wet with invasive attacks, part 1: Target recon </a>
<li><a href="http://siliconexposed.blogspot.co.uk/2014/03/getting-my-feet-wet-with-invasive_31.html">Getting my feet wet with invasive attacks, part 2: The attack</a>
</ul>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-13978168045694056182014-01-11T22:00:00.001+00:002014-01-11T22:02:07.697+00:00Soft horizontal scrolling on the CPC FPGA<p>So, the previous post was a bit light on explanation. That's because it wasn't quite working properly, although I've had a chance to fix it up and now it's a lot better, so I've just updated the picture. So, what does it represent?
</p><p>
Perhaps the best explanation is by way of a quick demo:
</p><p>
<iframe width="853" height="480" src="//www.youtube.com/embed/9mOMSfXha48" frameborder="0" allowfullscreen></iframe>
</p><p>
Basically, makes CPC FPGA the easiest CPC hardware to use on an LCD TV. Normally, smooth horizontal scrolling looks awful on an LCD because the monitor reacts to the signal differently on an LCD to a CRT. Essentially this is because the PLL is tuned to the higher frequencies that monitors are usually used at and so they react to a moving horizontal sync pulse more rapidly.
</p><p>
Moving the sync pulse is a pretty bad thing to do as it's technically a non-conformant video signal - it's just that it works fine with the CPC monitor... and now with the CPC FPGA it works fine on an LCD TV too! :)
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-62500217559956256472014-01-04T02:07:00.002+00:002014-01-11T21:55:09.586+00:00Emulating deformed hsync pulses<img src="http://ranulf.net/fpga/IMG_20140111_200938_900.jpg" height="675" width="900" />
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-65031378265637514742013-12-31T10:41:00.001+00:002013-12-31T10:41:17.876+00:00Rewriting sidecar2 - much better JTAG speed now<p>
One of the key features of my FPGA board is the coprocessor - an Atmel ATmega32u2 running code I'd codenamed "sidecar". This is responsible for the USB interface to the PC and disk emulation.
</p>
<p>
Up until this point, my USB code was quite hacky - based on the LUFA example USBtoSerial example, it had a USB-serial bridge and also allowed JTAG operations using USB control messages. Unfortunately, the chip I'd chosen only supports a maximum of 4 endpoints and a virtual serial port requires 3 endpoints itself (actually, the FTDI chip only uses 2, but it consequently needs a driver as it's not a standard USB CDC device) and so there was little choice in the matter. And control messages seemed to work for the most part, but I'd often get random disconnects whilst programming the flash chip (originally, it was about 1 failure every 5 flash cycles so I wasn't too worried). As the code I was running on the Atmel was getting more and more complicated (it also handles FDC emulation and the SD card), this failure rate increased to the point where the majority of reflash cycles were failing.
</p>
<p>
So, this was annoying and I was also getting fairly poor performance from my JTAG interface - it'd take about 20 seconds to flash the PROM for instance, which for a 200KB file is pretty slow! In the mean time, I'd decided to research booting the FPGA over JTAG as then at least I wouldn't be pummelling the PROM with all these erase-write cycles.
</p>
<p>
So, you know from the previous post, I've had a lot of difficulty with this, ultimately it turns out that contrary to the Xilinx docs, JTAG mode isn't always available and as soon as you start configuring the chip, it resamples M0,M1,M2 and reads data from there (although unreliably as it seems to use the JTAG TCK as it's sample clock, but it's still feeding the PROM CCLK at a much faster rate). So, I hooked up a spare data pin from the Atmel to the M0 and M2 pads (which fortunately, I'd had the presence of mind to bring out to a jumper as I'd always planned to support JTAG boot). This didn't work either.
</p>
<p>
<img src="http://ranulf.net/fpga/img0068s.jpg" width="900" height="600" alt="See the jumper wire in red"/>
</p>
<p>
By chance I re-read the documentation and realised this pin was actually 2.5V level and so feeding it 3.3V from the Atmel, whilst not damaging the chip (fortunately) was causing erratic behaviour. I discovered that if I left the pins floating (I'd previously been pulling them to GND for PROM boot) then JTAG boot worked as the Xilinx chip actually contains pull-ups for these configuration pins. So far so good. However, I actually want the default option to be PROM boot and the Atmel takes a little time on boot before it can pull this pin low, so now the FPGA remains stubbonly uninitialised on power on. I tried having a pull-down resistor on these pins, but they fought with the pull-ups and put the voltage into the "not quite high, not quite low" territory, and whilst I could probably have won the battle by using a really low resistance pull-down, I didn't want the current loss when the Atmel was driving this high...</p>
<p>
Despite all this, even though I could now boot via JTAG, this process was still unreliable - the USB stack was still crashing randomly, and so the whole thing was really frustrating. I got so annoyed, I kind of ignored the project until this week of holiday over Christmas. I'd wanted to do the USB stuff by interrupt, but the LUFA docs specifically mention how support for this was removed and how polling was the only option. However, my curiousity was piqued when I found Jim Paris' source for <a href="https://git.jim.sh/jim/lufa-ftdi.git">lufa-ftdi</a> which emulates the functionality of an FTDI 2-endpoint serial port and does so solely through interrupts. I took a look, learned a lot more about the Atmel USB stack and started rewriting my sidecar code in a similar way.
</p>
<p>
So now, I have a rock solid JTAG implementation using 2 endpoints and because the whole process is optimised to use ping-pong buffers, it means I can do a 128-bit JTAG exchange per USB packet. Because these are bulk endpoints too, there can be more than one in a 1ms period, and because I'm using ping-pong buffers, I can be reading from a receive buffer (OUT), bit-banging the JTAG exchanging and writing to the transmit buffer (IN), whilst the PC is still reading the previous result (IN) buffer. Pretty sweet. Now, I can write the PROM in 8 seconds and what's more, the JTAG boot works reliably and boots in under 5 seconds.
</p>
<p>
I'm probably going to drop the serial port functionality, just because serial ports weren't really all that common on the CPC anyway, and I'm exploring the possibility of reconfiguring the USART into SPI-master mode and doing 8-bits of JTAG exchange that way instead which would further increase the speed.
</p>
<p>
Another casualty of this rewrite is that I've lost all my old FDC emulation and FAT code. The FDC code needed rewriting as its state machine was pretty buggy, but this is the next thing on the horizon now... :)
</p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-12952808681529061262013-11-25T12:59:00.001+00:002013-11-25T12:59:10.111+00:00Booting an FPGA image over JTAGI've been trying to get this working all weekend without success. It's incredibly frustrating as so many things seem to be "almost working" - after loading an image via JTAG, I can probe the USERCODE and even interact with my own BSCAN device and it seems to work, but seemingly everything else is inoperative, so no video out etc seemingly no activity on the IO pins...
Today, I just found this <a href="http://www.xilinx.com/support/answers/22255.htm">wonderful snippet</a> via <a href="http://www.pender.ch/faq.shtml#faq17">here</a>:
<br />
<blockquote>
<h3>Explanation of the problem:</h3>
The problem is that iMPACT causes the mode pins to be sampled. If the device is in master mode, the CCLK is produced and the PROM begins to load the device with data. This occurs before iMPACT issues the instruction to begin configuration. When this happens, the JTAG logic gains control over the configuration logic and loads the device with the bitstream. The fabric of the Spartan-3/-3E FPGA must be initialized before it can be written over, so frames that have been written to by the PROM will not configure correctly. The CRC check passes as this occurs, while data is passed into the device.
The device goes through the start-up sequence, DONE goes High, and the device becomes operational. The problem is that the first few frames of the device have been corrupted and the design might not work successfully, and a verify with iMPACT fails.
<h3>Work-around</h3>
Erase the flash or change the Mode pins to JTAG to work around this issue. </blockquote>
So, it seems that the only way to get this to work is to not drive the M0, M2 high. Fortunately, my latest board I was contemplating driving it only by JTAG and so M2 and M0 are brought out to a single jumper, so the boot modes can be either "000" or "101". I guess I could expose this to a pin on the Atmega in a future board... :)Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-3398473578404270792013-09-11T12:34:00.001+01:002013-09-12T00:09:40.707+01:00Fractals all the way down<p>"Fractals all the way down" came 2nd in the Wild compo at Sundown 2013. The pouët page for the demo is <a href="http://www.pouet.net/prod.php?which=61862">here</a>.
</p>
<iframe width="420" height="315" src="//www.youtube.com/embed/krTd4oCPblk" frameborder="0" allowfullscreen></iframe>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-65174514792069956532013-09-08T01:00:00.000+01:002013-09-08T01:00:46.175+01:00FPGA demo at Sundown 2013<p>So, I took a bit of a break from my Amstrad CPC core and made an FPGA only demo for the CPC2013 board. I haven't sorted out a video capture yet, but here's a little picture:</p>
<p>
<a href="http://ranulf.net/IMG_20130907_081406.jpg"><img src="http://ranulf.net/IMG_20130907_081406.small.jpg"/></a>
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-90412134593035884962013-08-03T18:58:00.001+01:002013-08-03T19:00:16.146+01:00Slow news month(s)<p>
So, not much visible progress has been made over the last couple of months...
</p><p>
The laser cut case from the last video fit pretty well, as you can see them here:
</p><p>
<a href="http://ranulf.net/fpga/IMG_0035.JPG"><img src="http://ranulf.net/fpga/IMG_0035s.JPG" width="720" height="480"/></a>
<a href="http://ranulf.net/fpga/IMG_0036.JPG"><img src="http://ranulf.net/fpga/IMG_0036s.JPG" width="720" height="480"/></a>
</p><p>
I would like to tighten up the holes a little so that the board doesn't rattle around when the PCB doesn't have feet attached, but it's still a pretty good second effort. Sadly, it looks like I won't be making any more cases for a while - fizzpop moved to their own building, so no longer has access to the laser cutter I used before. There are plans to buy one in the near future, but that'll be a few months off. And besides, I seem to be too busy doing other things to actually make it along anyway!
</p><p>
I've been (silently) working on the FDC emulation (which I decided to do on the Atmega side) - a first version works, but it's a bit buggy. It manages to load a few demos, but it's nowhere near stable enough to release publically.
</p><p>
I've also been trying to get the DVI transmitter chip to work. It looks like I forgot a couple of connections to the chip, although often fixing them up I still can't get the chip to actually transmit any data. It's hard to tell where the problem lies, sadly, so it might still be some time before I get DVI output working...
</p><p>
So today, I decided to investigate how many shades I can coax my 2-bit DACs to produce... I'll give you a clue, it's more than 4! :) There are about 30, although quite a lot of them are difficult to discern, but it looks like there are enough shades to produce the equivalent of a 4-bit DAC. I took some pictures so I can analyse them better:
</p><p>
<img src="http://ranulf.net/fpga/IMG_0042s.JPG" width="720" height="480"/>
<img src="http://ranulf.net/fpga/IMG_0043s.JPG" width="720" height="480"/>
<img src="http://ranulf.net/fpga/IMG_0044s.JPG" width="720" height="480"/>
<img src="http://ranulf.net/fpga/IMG_0045s.JPG" width="720" height="480"/>
</p><p>
The other big news is that I've got a new job, starting in 2 weeks. I guess that might mean I get even more busy though...
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-38489170779713017562013-05-23T00:11:00.000+01:002013-05-23T00:11:45.778+01:00Laser cutting a new case and other news<p>
I've mostly spent the last couple of weeks making a start on the floppy disk emulation code. I decided to move most of the complex code that dealt with the FAT filesystem away from the FPGA as the state machine was getting very large and consuming lots of resources, and instead having it running on the Atmega support processor (which is fine because it's mostly idle unless being used as a USB to FPGA bridge and I've got about 14KB of flash ROM unused).
</p>
<p>
I've now fully encapuslated the IO between the two sides with a nice reliable protocol based on SPI where the different sides switch between being master and slave so that the AVR can be woken up by interrupt when the disk starts being used but then gain control so it's can manage the data transfer so that no bytes get dropped (as they might if the FPGA was the SPI master). So, now, I have the FPGA-AVR communication code working, the AVR handling the FAT meta data, so I just need to stick the disk image format code in... :)
</p>
<p>
And tonight, I was back at fizzpop after a couple of weeks of not being able to make it along. Here's a video of me cutting a redesigned version of the case to hold the CPC2013 board:</p>
<iframe width="560" height="315" src="http://www.youtube.com/embed/WOd5p3fxUzc" frameborder="0" allowfullscreen></iframe>
<p>
It seems that the holes are almost in the right place this time - I'll post pictures in the morning, but the acrylic is currently out in the porch until the smell dissipates a bit...
</p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-18057786671246572942013-05-02T09:22:00.002+01:002013-05-02T09:23:38.468+01:00Prototype case<p>
I made a prototype version of a case for the CPC2013 last night at <a href="http://www.fizzpop.org.uk/">fizzpop</a> using the laser cutter:
</p>
<a href="http://ranulf.net/fpga/IMG_20130502_091125.jpg" imageanchor="1" ><img border="0" src="http://ranulf.net/fpga/IMG_20130502_091125.jpg" width="816" height="612"/></a>
<p>
It's a little too small for the PCB, the holes aren't quite in the right place and a couple of them are missing as I forgot to convert the circles into bezier paths. But hopefully, armed with the knowledge that it can actually be done I'll be able to get it right next week... :)
</p>
<p>
The case is based on the <a href="http://www.thingiverse.com/thing:24461">Adafruit Raspberry Pi design at thingiverse</a> which seems suspiciously similar to one I bought on ebay! My modifications are available in <a href="https://github.com/ralferoo/cpc2013-case">my github repository</a>...
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com1tag:blogger.com,1999:blog-2541933305981196398.post-891942363413512062013-03-28T19:49:00.003+00:002013-03-28T19:49:32.726+00:00First of my revision 2 PCBsMostly working well. There's a couple of minor mistakes, but everything mostly seems to work insofar as I've tested it. Annoyingly, I ordered the wrong size oscillators after sending off the PCBs, so the wires are heading off to the master 16MHz clock. Amazingly, there doesn't seem to be any interference!
<br/>
<a href="http://www.ranulf.net/fpga/img_9983-small.jpg" imageanchor="1" ><img border="0" src="http://www.ranulf.net/fpga/img_9983-small.jpg" /></a>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-80091691944531815392013-03-11T10:18:00.001+00:002013-03-11T10:18:15.358+00:00Updated revision 2 schematicsMy friend reenigne suggested I have separate audio and video ground paths, so I've made that change and decided to do the same with the USB ground, even though it wasn't explicitly required.
<p>
Hopefully this will all work now, I've sent them off to be fabbed! <tt>\o/</tt>
<p>
<a href="http://ranulf.net/fpga/homeboard99.top.png" imageanchor="1" ><img border="0" src="http://ranulf.net/fpga/homeboard99.top.png" /></a>
<p>
<a href="http://ranulf.net/fpga/homeboard99.bottom.png" imageanchor="1" ><img border="0" src="http://ranulf.net/fpga/homeboard99.bottom.png" /></a>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-11047322194811383362013-03-09T20:47:00.000+00:002013-03-09T20:47:20.274+00:00I think I've finished the revision 2 board layoutSo, I've been <b>VERY</b> quiet recently. It's not that I've not been doing anything on this project. Quite the opposite...
<p>
After quite a few late nights, I <b>think</b>, or at least <i>hope</i>, I've finished my new board layout. I can't see anything obviously wrong with it, but neither did I before I found a very obvious error about an hour ago... :o
<p>
<a href="http://ranulf.net/fpga/homeboard96.top.png" imageanchor="1" ><img border="0" src="http://ranulf.net/fpga/homeboard96.top.png" /></a>
<p>
<a href="http://ranulf.net/fpga/homeboard96.bottom.png" imageanchor="1" ><img border="0" src="http://ranulf.net/fpga/homeboard96.bottom.png" /></a>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-48609402141668074412013-03-04T09:20:00.003+00:002013-03-04T09:21:05.568+00:00Busy doing a new layout<p>So, I've been pretty quiet recently apart from posting a few links. I'm actually busily routing revision 2 of my board and hoping I'll be able to send it off this week to have some made up. Hopefully this will fix all the issues I found on the previous board as well as having a lot more expansion options...
</p><p>
I'll post some pictures when it's finished! :)
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-77646831351237005322013-02-28T08:50:00.001+00:002013-02-28T08:51:49.020+00:00Ken Shiriff's blog<p>
I've raised awareness of this blog over at CPCwiki, but it's well worth checking out <a href="http://www.righto.com/">Ken Shiriff's blog</a>.
</p>
<p>
Just recently, he's been looking at the <a href="http://www.righto.com/2013/01/notes-on-pla-on-8085-chip.html">PLA that deals with the decoding of 8085 opcodes</a>, and has an excellent way of presenting the <a href="http://www.righto.com/2013/02/8085-instruction-set-octal-table.html">8085 instruction set in Octal</a>:<br/>
<img src="http://ranulf.net/fpga/8085_octal.png" width="688" height="316"/>
</p>
<p>
As the Z80 is a very close relative, I'd say it's well worth keeping an eye out on this very well written blog. The technical discussion of the <a href="http://www.righto.com/2013/02/looking-at-silicon-to-understanding.html">8085 undocumented flags</a> is outstanding - he reverse engineers the flags from looking at a photo of the silicon, translates that into gates, works out why the existing documentation is wrong and what the flags can be used for.
</p>
<p>
It's worth remembering that the 8085 is somewhat different to the Z80, however. It's still a fascinating chip to look at and by looking at the differences between the two and how they diverged from a common ancestor is very revealing.
</p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-61008127335779181472013-02-05T21:26:00.003+00:002013-02-05T21:26:36.441+00:00Reading the FAT the BASIC way...<p>
So, I've knocked together a simple SD card interface... There's a state machine which initialises the card (works with MMC, SD and SDHC), reads the partition table and then exposes a simple byte-wise interface, handling all the sector blocking stuff automatically. You simply pass in the sector and offset, assert begin_read and the card layer asserts data_ack when the data is available to be read on data_out. Then deassert begin_read and wait for data_ack to deassert before continuing.
</p>
<img src="http://ranulf.net/fpga/IMG_20130205_210621.jpg" width="816" height="612"/>
<p>
I've just made a very simple interface from this to the CPC. Writing to &FAD0 shifts a byte into the sector address and resets the sector offset. Reading from &FAD0 asserts begin_read and returns data_ack in the top bit. Reading from &FAD1 fetches the data input and de-asserts begin_read. Simples!
</p>
<p>
I need to build a FAT layer on top of this and then I can build the DSK image layer on top of that. But for now, I just wanted to get to work on the DSK layer code, so I'm going to use the interface so far to read the file into RAM.
</p>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-5860528564660087732013-01-21T08:07:00.001+00:002013-01-21T08:07:21.923+00:00ROM and RAM bankingJust made a quick video this morning which demonstrates the newly added ROM and RAM bank features.
<br/>
Previously I was emulating just 64KB of RAM and copying ROM images into the spare RAM. Now, the flash ROM is accessed in-place allowing me to expose the extra RAM as an expansion board.
<br/>
<iframe width="560" height="315" src="http://www.youtube.com/embed/PkiFJyQhkuU" frameborder="0" allowfullscreen></iframe>Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com0tag:blogger.com,1999:blog-2541933305981196398.post-59095908525087127682013-01-11T22:45:00.000+00:002013-01-11T22:47:06.713+00:00Sounds and tapes and clocks, oh my!<p>
So, with a bit of experimentation I discovered that dropping R19 down to about 8000 ohm fixes the tape input. Not only are the tape signal high/low bars equally sized now , it also sounds right when it's loading instead of the weird "high frequency" noises in the previous video. Here's an updated schematic where I've just added a 47K resistor R61 in parallel with R19 to drop it to approximately the right value:
<br/>
<img src="http://www.ranulf.net/fpga/tape_input_upd.png" width="558" height="235" />
</p>
<p>
I've also been learning over the last week about the importance of clock domains, more specifically the scarceness of global clocks. It seems doing innocent things like this will introduce severe unpredictability:
<pre style="background: #202020; border: 1px solid #404040;">
if rising_edge(hsync) then
...
something <= '1';
...
end if;
</pre>
Obviously, this introduces a D flip-flop clocked on hsync. However, what this actually seems to do is put this into a pool of things that might be promoted to a global clock or might be routed all over the place. At first, everything seems to work fine and then suddenly, changing a small bit of code somewhere causes resources to be placed slightly differently which causes a different selection of clocks to be promoted to be global clocks.
</p>
<p>
Around the time I started using the DCM to generate a 32MHz clock from the standard 16MHz clock, I'd forced most of important clocks to be globals using <b>BUFG</b>, but I hadn't realised how unpredictable all the innocent looking clocks like the one above would be. Something trivial like changing the RAM banking logic would cause glitches in the CRTC (e.g. bit 2 of the width register always being set) or even complete screen failure.
</p>
<p>
So, what's the solution? It actually turns out that if you stick to only ever using a small number of clocks (there's 8 global clock lines on all the Spartan 3 chips), then everything works completely as expected. Replacing the multitude of clocks actually turns out to be remarkably easy, e.g.
<pre style="background: #202020; border: 1px solid #404040;">
if rising_edge(clk32) then
if hsync='1' and hsync'last_value='0' then
...
something <= '1';
...
end if;
end if;
</pre>
It turns out that you end up needing very few clocks. I've gone from having too many clocks that the assignments were random, to only 5 clocks in total: 32MHz, 32MHz @ 180°, 16MHz, 1MHz (for CRTC/PSG) and 4MHz (for Z80).
</p>
<p>
The best result of this is that this fixing these clock issues also fixed a critical problem with the sound emulation. I'd noticed some glitches before with a couple of songs, e.g. the fantastic <a href="http://youtu.be/7GiXrGjUgdE?t=18m35s">Hyperdragon by Reed/Fairlight</a>, but I hadn't ever managed to figure out what was wrong. What was happening was due to this clock issue the first sample in each envelope was actually played with the volume of the last sample in that envelope. This was due to audio clock no longer being a global clock, so the audio events had stopped being precisely synchronised and the envelope counter was being reset 1/16 envelope period after it was being used. So, BASIC which didn't use envelopes was fine and most songs sounded fine, but some of the drum effects sounded very odd in others. I'll upload a video of this soon, but my phone just ran out of battery as I was recording a demo for the blog...
</p>
Ralfhttp://www.blogger.com/profile/10844724134361778460noreply@blogger.com1