So, this article that I was rambling about last night / this morning...
Advanced Synthesis Techniques argues the merits of
Sequential versus Parallel in VHDL code by using the example of a UART. Coincidentally, that's exactly the program I was trying to solve... Actually, I spotted my stop bit error by reading this, although I still reimplemented the UART myself rather than copying his because I want mine to be driven by the master 16MHz clock, not the transmit speed clock, but after rewriting my implementation using things I'd learned in this guide it worked... first time!
I came to this via
Mike Tresler's pages which are also worth perusing...
Random thought... I'm still using a signal and determining the current state based on the bits counter being 0 rather than the state engine he proposed. I just realised that doing that introduces a lot more gates than having a latch on a single bit to determine state... I obviously still need to readjust my mindset to VHDL some more...
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