SRAM board

So, I've built a SRAM / flash module:


I've pretty much started again from scratch with my FPGA design because I was getting lots of errors about global clocks when I was synthesizing. I started again with just a single 16MHz clock generated by the PLL from the 20MHz input. I then added the T80 soft-core from opencores.

My main problem with this was the Actel synplify tool was aggressively optimising the design and turning the T80_Regs.vhd into an SRAM block, which manifested itself with things appearing to work, but subtleties in the ALU appearing, e.g. "INC HL" would be act like "HL=BC+1". The problem is that the register file is triple-ported on output, which clearly won't work with the SRAM block that got synthesized. More annoyingly, even after removing the vectors and producing a complicated set of case statements to multiplex writing and reading to these registers, it still realised it was effectively a RAM and decided to migrate it to one of the SRAM units. This was annoying as it took about 8 hours for me to figure out what was going wrong and how to coax synplify to not destroying my design. The solution btw looks like this:

attribute syn_ramstyle : string;
attribute syn_ramstyle of reg0h, reg0l, ... reg7h, reg7l : signal is "registers";

Obvious, huh?

Anyway, with that out of the way and my serial port (mostly) working, I plucked up the courage to hook in my SRAM module. It didn't work. My experiment with heat-gun soldering the edge connectors didn't work and there was still unmelted solder shorting some of the pins underneath the mound of flux gunk. I removed the chip (my design meant that the edge connector was covered by the SRAM chip) and tidied this up before reattaching the chip with an iron this time. It worked! BTW: the heat gun is awesome for removing things... :)

So far, I've not hooked up the flash ROM yet as I need to built an SPI interface and I want to fix up the serial output because occasionally I get corrupt data (maybe 1 character in 1000), but here's a video showing the SRAM being initialised and then incremented in a pattern:



The ROM data by the way is hard coded. There's a makefile which uses pasmo to assemble to binary and from there I've got a python script to create a big VHDL case statement. I'll be using something similar to bootstrap the RAM with contents from the SPI flash rather than directly accessing the flash as it's needed - I think that will introduce too many wait states and I want the CPU to be able to access the SPI bus anyway so data can be put onto the flash chip by the Z80...