As you can see, it's pretty handy having my SREC loader as I can just load in a raw binary file to screen memory. :) There are a few things left to do with the gate array, such as the interrupt generation and ROM banking, and then to be at the basic CPC 464 state I just need to implement the AY-8912 and the PPI chip (or at least the keyboard part). I guess that means I need to dig out my soldering iron to build a PS/2 keyboard interface and level converter (the FPGA is 3.3v IO, the PS/2 port is 5v).
Sunday, 8 January 2012
gate array video output
So now I've got the video data being decoded correctly and going through the CLUT in the gate array in all 3 video modes:



As you can see, it's pretty handy having my SREC loader as I can just load in a raw binary file to screen memory. :) There are a few things left to do with the gate array, such as the interrupt generation and ROM banking, and then to be at the basic CPC 464 state I just need to implement the AY-8912 and the PPI chip (or at least the keyboard part). I guess that means I need to dig out my soldering iron to build a PS/2 keyboard interface and level converter (the FPGA is 3.3v IO, the PS/2 port is 5v).
As you can see, it's pretty handy having my SREC loader as I can just load in a raw binary file to screen memory. :) There are a few things left to do with the gate array, such as the interrupt generation and ROM banking, and then to be at the basic CPC 464 state I just need to implement the AY-8912 and the PPI chip (or at least the keyboard part). I guess that means I need to dig out my soldering iron to build a PS/2 keyboard interface and level converter (the FPGA is 3.3v IO, the PS/2 port is 5v).
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