Multiplexing video and CPU access

Of the roles the gate array performs in the CPC range, memory multiplexing is the most important. What it does is insert wait states so that the CPU only ever accesses memory 1 cycle in every 4, and using the 2 of the remaining 3 to read memory for video display.

After being plagued with subtle timing issues for a while, the view here of the simulator is left from the point when I realised my emulation of this might actually be working:



After the 7 minutes of compile time, I finally got to see it working... :)



Most of the problems were actually a complete lack of documentation for the opencores.org T80 softcore I'm using. There's a couple of parameters you specify when creating an instance and in a couple of significant areas it defaults to being almost, but slightly different to the Z80 timing diagrams...

Next up... decoding the pixel data correctly and adding the CLUT. After that, I'll work on memory banking and trying to use the flash chip.