Meeting new people and progress on the atmega loader

On Wednesday evening, I decided to venture into Birmingham to visit a hackspace I'd found online, fizzpop which coincidentally has just moved to the Black Country Atelier premises. Even though I'd printed out a map and had a rough idea of where I was going, I foolishly trusted the satnav which twice took me into the very middle of city centre from different directions, getting me lost each time before I eventually decided to just ignore it, checking the printed map at every red light instead.

Anyway, there were about 10 other people there, and there seemed to be a healthy interest in a bunch of areas. I started off looking at one guy's MakerBot 3D printer which was pretty interesting, but soon realised that almost everybody had wandered off for instruction on how to use the laser cutter. I caught the last half of the safety briefing and watched a couple of pieces of acrylic get cut up at different laser strengths and speeds as a demo. Later on, a couple of the guys etched a QR barcode into some transparent acrylic and burnt the same barcode onto some wood. Both turned out really well.

I'd take along my fpga board, as I wasn't really sure what to expect of the evening but figured I could always hack some more on the AVR code I'd given up on when it seemed to stop working. I didn't actually spend much time at all coding during the evening, but I did notice that the debug data did actually seem to suggest the JTAG chain was working, even though the code didn't work. I kind of knew that as it was previously working and then stopped, but it piqued my interest a bit more. After running some test patterns, I noticed that they were more often than not getting corrupted.

For some reason I woke up really early this morning, and decided to take another look. There were two problems, all within about 3 lines of each other... and in the most fundamental function in my code - the one that clocks in and out a bit of JTAG data! I was reading the TDO before pulsing the clock high and low, as per the spec, and pausing for a few cycles to bring my JTAG clock speed down to about 1MHz. However, because this function was inlined, in a lot of cases where multiple bits are written to change state, there wasn't sufficient delay in the TCK low state before the next bit was written out. So, what worked fine when only the PROM was in the chain (which supports a 33MHz JTAG clock) failed completely when the FPGA itself (which only supports a 25MHz JTAG clock).

Unfortunately, now most of my good JTAG test code, including all the boundary scan test suite is written for the Raspberry Pi GPIO pins, but I think I'll add another command to the AVR code to allow JTAG over serial so I can run my boundary scan code on the PC via the AVR.

I've also opened up the source for the schematic and all JTAG code to date, so this is now available on github.