So, I've got the CRTC working. That was actually pretty painless and got it working in a couple of hours early New Year's Eve. So, that was 2 days ago. I can't have just been sat on my backside ever since! Well, apart from a nice bike ride today, I have in fact been busy.
I spent most of yesterday trying to reverse engineer what the gate array actually does to multiplex the RAM access. After a lot of time working out potential scenarios by poring over the Z80 datasheet diagrams and T-state breakdowns compared to the actual CPC instruction timings, it became apparent that it all works out pretty easy if the video uses cycles T1 and T3 (when considered as an instruction fetch) and adds a wait state after T2 in a normal read/write cycle and latching the read data even though we already have it available so we can present it at the end of T3, it all works out nicely. In fact, I'm not even sure why Amstrad also add a delay cycle to IO requests as they don't cause RAM collisions...
Anyway, with all that figured out, I started trying to implement the gate array. Getting the video memory accesses working was kind of simple, although I haven't implemented the pixel decoding yet, so instead I'm just outputting them as raw 2-bit RGB data. Actually, this mode looks kind of cool, so I might implement this as a special feature anyway:
What's a bit trickier is that I've managed to bugger up the Z80's access to memory in the process. It's close, very very close, but just after the OUT instruction the delayed refresh triggers my latch logic and I start an extra fake memory request. Actually, just describing this make me confident I've seen the problem. Tools like the VHDL simulator are awesome, though. Kids these days don't know how lucky they are! Here's the point where it all goes wrong!