So, it's been 10 days since I sent my prototype board off to be made up. I guess I've got at least another 2 weeks to wait, so it'll be a bit quiet here for a while.
I was pointed to this blog which is pretty interesting and talks about some similar timing and signal noise problems to what I used to see on one of my earlier PCBs: Veronica - VRAM.
Also, over the Easter weekend I went to Revision in Saarbrucken. Unfortunately, I'd spent so much time designing this PCB that I'd not had chance to code anything demowise, but it was still nice to pull out the assembler and do some pure software development over the weekend. I've found away to speed up something I http://www.blogger.com/img/blank.gifwas working on last year, although ihttp://www.blogger.com/img/blank.gift'll involve a lot of meticulous cycle counting.
There were 2 very good demos by Benediction, and I also spent a while chatting to these guys which was great as it's the first party I've been to where I've actually found any fellow CPC coders! Krusty also gave an overview presentation on the CPC which will have helped to make more people aware of the CPC. Anyway, their demos are here (and both came 3rd in their respective categories too which was aweseome given the competition):
and Stop that nyan cat!:
One final project that was phenomenal was lft's Parallelogram demo running on an FPGA that won the wild competition:
I had a few good conversations about my FPGA here too - it seems a lot of people are interested in this.