So, it seems that the only way to get this to work is to not drive the M0, M2 high. Fortunately, my latest board I was contemplating driving it only by JTAG and so M2 and M0 are brought out to a single jumper, so the boot modes can be either "000" or "101". I guess I could expose this to a pin on the Atmega in a future board... :)
Explanation of the problem:The problem is that iMPACT causes the mode pins to be sampled. If the device is in master mode, the CCLK is produced and the PROM begins to load the device with data. This occurs before iMPACT issues the instruction to begin configuration. When this happens, the JTAG logic gains control over the configuration logic and loads the device with the bitstream. The fabric of the Spartan-3/-3E FPGA must be initialized before it can be written over, so frames that have been written to by the PROM will not configure correctly. The CRC check passes as this occurs, while data is passed into the device. The device goes through the start-up sequence, DONE goes High, and the device becomes operational. The problem is that the first few frames of the device have been corrupted and the design might not work successfully, and a verify with iMPACT fails.
Work-aroundErase the flash or change the Mode pins to JTAG to work around this issue.
Monday, 25 November 2013
Booting an FPGA image over JTAG
I've been trying to get this working all weekend without success. It's incredibly frustrating as so many things seem to be "almost working" - after loading an image via JTAG, I can probe the USERCODE and even interact with my own BSCAN device and it seems to work, but seemingly everything else is inoperative, so no video out etc seemingly no activity on the IO pins... Today, I just found this wonderful snippet via here: