Why you should write an emulator

Here's my talk from Revision 2015:

There's also a whole load of other seminars and compos to watch too... :)

Breaking baud video

Breaking Baud... just realised that it's almost a year after the fact and I've still not uploaded a proper capture of the final version of Breaking Baud. So, the best quality capture is still the official livestream... :)

Seminar at Revision 2015

Eeeks, so I realised that I've been too busy to post a single blog entry since Revision last year. Ooops! Anyway, today I presented a seminar at this year's Revision called "Why you should make an emulator". I'll provide a youtube link when available, but for now you can check out the slide deck and just imagine that it's the best presentation you've ever heard! :)

Breaking Baud - 2nd place in the Revision Oldskool demo competition

So, one of the reasons I've not been making much progress recently on the FPGA is that I've spent the last couple of months working on a new tape turbo load system for the Amstrad CPC.

The result is here (warning, don't turn up too loud until you get a feel for the volume of the loading sounds!):

I'm proud to say it came 2nd in the Oldskool competition, stacked up against some very worthy competition. Many thanks to JulijanaM and rexbeng for their beautiful artwork and McKlain for his amazing tunes!

Silicon exposed blog

I've just discovered these awesome posts via Hackaday:

• Getting my feet wet with invasive attacks, part 1: Target recon
• Getting my feet wet with invasive attacks, part 2: The attack

Soft horizontal scrolling on the CPC FPGA

So, the previous post was a bit light on explanation. That's because it wasn't quite working properly, although I've had a chance to fix it up and now it's a lot better, so I've just updated the picture. So, what does it represent?

Perhaps the best explanation is by way of a quick demo:

Basically, makes CPC FPGA the easiest CPC hardware to use on an LCD TV. Normally, smooth horizontal scrolling looks awful on an LCD because the monitor reacts to the signal differently on an LCD to a CRT. Essentially this is because the PLL is tuned to the higher frequencies that monitors are usually used at and so they react to a moving horizontal sync pulse more rapidly.

Moving the sync pulse is a pretty bad thing to do as it's technically a non-conformant video signal - it's just that it works fine with the CPC monitor... and now with the CPC FPGA it works fine on an LCD TV too! :)

Emulating deformed hsync pulses